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LTC2421/LTC2422 1-/2-Channel 20-Bit Power No Latency TMADCs in MSOP-10
FEATURES
s s s s s s
DESCRIPTIO
s s s s s
s s s s
s
20-Bit ADCs in Tiny MSOP-10 Packages 1- or 2-Channel Inputs Single Supply 2.7V to 5.5V Operation Low Supply Current (200A) and Auto Shutdown Automatic Channel Selection (Ping-Pong) (LTC2422) No Latency: Digital Filter Settles in a Single Conversion Cycle 8ppm INL, No Missing Codes 4ppm Full-Scale Error 0.5ppm Offset 1.2ppm Noise Zero Scale and Full Scale Set for Reference and Ground Sensing Internal Oscillator--No External Components Required 110dB Min, 50Hz/60Hz Notch Filter Reference Input Voltage: 0.1V to VCC Live Zero--Extended Input Range Accommodates 12.5% Overrange and Underrange Pin Compatible with LTC2401/LTC2402
The LTC(R)2421/LTC2422 are 1- and 2-channel 2.7V to 5.5V micropower 20-bit analog-to-digital converters with an integrated oscillator, 8ppm INL and 1.2ppm RMS noise. These ultrasmall devices use delta-sigma technology and a new digital filter architecture that settles in a single cycle. This eliminates the latency found in conventional converters and simplifies multiplexed applications. Through a single pin, the LTC2421/LTC2422 can be configured for better than 110dB rejection at 50Hz or 60Hz 2%, or can be driven by an external oscillator for a user defined rejection frequency in the range 1Hz to 120Hz. The internal oscillator requires no external frequency setting components. These converters accept an external reference voltage from 0.1V to VCC. With an extended input conversion range of -12.5% VREF to 112.5% VREF (VREF = FSSET - ZSSET), the LTC2421/LTC2422 smoothly resolve the offset and overrange problems of preceding sensors or signal conditioning circuits. The LTC2421/LTC2422 communicate through a 2- or 3-wire digital interface that is compatible with SPI and MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S
s s s s s s s
Weight Scales Direct Temperature Measurement Gas Analyzers Strain Gauge Transducers Instrumentation Data Acquisition Industrial Process Control
TYPICAL APPLICATIO
2.7V TO 5.5V 1F 1 VCC LTC2422 REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET - 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET - ZSSET) 0V TO FSSET - 100mV 2 3 4 5 FSSET CH1 CH0 ZSSET SCK SDO CS GND FO
Pseudo Differential Bridge Digitizer
2.7V TO 5.5V
VCC
10
= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
9 8 7 3-WIRE SPI INTERFACE
6
24212 TA01
U
1 2 4 3 5 VCC LTC2422 FSSET 9 SCK CH0 CH1 ZSSET GND 6 SDO CS FO 8 7 10 INTERNAL OSCILLATOR 60Hz REJECTION 3-WIRE SPI INTERFACE
24012TA02
U
U
24212f
1
LTC2421/LTC2422
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) to GND .......................- 0.3V to 7V Analog Input Voltage to GND ....... - 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V)
PACKAGE/ORDER INFORMATION
ORDER PART NUMBER
TOP VIEW VCC FSSET VIN NC ZSSET 1 2 3 4 5 10 9 8 7 6 FO SCK SDO CS GND TOP VIEW
LTC2421CMS LTC2421IMS MS10 PART MARKING LTUX LTUY
MS10 PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 130C/W
Consult factory for parts specified with wider operating temperature ranges.
CONVERTER CHARACTERISTICS The q denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. VREF = FSSET - ZSSET. (Notes 3, 4)
PARAMETER Resolution No Missing Codes Resolution Integral Nonlinearity Offset Error Offset Error Drift Full-Scale Error Full-Scale Error Drift Total Unadjusted Error Output Noise Normal Mode Rejection 60Hz 2% Normal Mode Rejection 50Hz 2% Power Supply Rejection, DC Power Supply Rejection, 60Hz 2% Power Supply Rejection, 50Hz 2% 0.1V FSSET VCC, ZSSET = 0V (Note 5) FSSET = 2.5V, ZSSET = 0V (Note 6) FSSET = 5V, ZSSET = 0V (Note 6) 2.5V FSSET VCC, ZSSET = 0V 2.5V FSSET VCC, ZSSET = 0V 2.5V FSSET VCC, ZSSET = 0V 2.5V FSSET VCC, ZSSET = 0V FSSET = 2.5V, ZSSET = 0V FSSET = 5V, ZSSET = 0V VIN = 0V (Note 13) (Note 7) (Note 8) FSSET = 2.5V, ZSSET = 0V, VIN = 0V FSSET = 2.5V, ZSSET = 0V, VIN = 0V, (Notes 7, 15) FSSET = 2.5V, ZSSET = 0V, VIN = 0V, (Notes 8, 15)
q q q
CONDITIONS
q q q q q
2
U
U
W
WW
U
W
(Notes 1, 2)
Operating Temperature Range LTC2421/LTC2422C ................................ 0C to 70C LTC2421/LTC2422I ............................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER
VCC FSSET CH1 CH0 ZSSET 1 2 3 4 5 10 9 8 7 6 FO SCK SDO CS GND
LTC2422CMS LTC2422IMS MS10 PART MARKING LTUZ LTVA
MS10 PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 130C/W
U
MIN 20 20
TYP
MAX
UNITS Bits Bits
4 8 0.5 0.04 4 0.04 8 16 6 110 110 130 130 100 110 110
10 20 10 10
ppm of VREF ppm of VREF ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF VRMS dB dB dB dB dB
24212f
LTC2421/LTC2422
A ALOG I PUT A D REFERE CE
SYMBOL VIN FSSET ZSSET CS(IN) CS(REF) IIN(LEAK) IREF(LEAK) PARAMETER Input Voltage Range Full-Scale Set Range Zero-Scale Set Range Input Sampling Capacitance Reference Sampling Capacitance Input Leakage Current Reference Leakage Current CS = VCC
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VREF = FSSET - ZSSET. (Note 3)
CONDITIONS (Note 14)
q q q
VREF = 2.5V, CS = VCC
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK High-Z Output Leakage SDO (Note 9) IO = - 800A IO = 1.6mA IO = - 800A (Note 10) IO = 1.6mA (Note 10) CONDITIONS 2.7V VCC 5.5V 2.7V VCC 3.3V 4.5V VCC 5.5V 2.7V VCC 5.5V
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
MIN
q q q q q q
2.7V VCC 5.5V (Note 9) 2.7V VCC 3.3V (Note 9) 4.5V VCC 5.5V (Note 9) 2.7V VCC 5.5V (Note 9) 0V VIN VCC 0V VIN VCC (Note 9)
POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q
CS = 0V (Note 12) CS = VCC (Note 12)
U
UW
U
U
U
U
U
MIN ZSSET - 0.12VREF 0.1 + ZSSET 0
TYP
MAX FSSET + 0.12VREF VCC FSSET - 0.1
UNITS V V V pF pF
1 1.5
q q
-100 - 100
1 1
100 100
nA nA
TYP
MAX
UNITS V V
2.5 2.0 0.8 0.6 2.5 2.0 0.8 0.6 -10 -10 10 10 10 10
V V V V V V A A pF pF V
q q q q q
VCC - 0.5 0.4 VCC - 0.5 0.4 -10 10
V V V A
MIN 2.7
TYP
MAX 5.5
UNITS V A A
24212f
q q
200 20
300 30
3
LTC2421/LTC2422 TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time FO = 0V FO = VCC External Oscillator (Note 11) Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 9) (Note 9) (Note 9) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 9)
q q q q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q q q q q q
fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7 to 5.5V unless otherwise specified. Input source resistance = 0. Note 4: Internal Conversion Clock source with the FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz 2% (external oscillator). Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz 2% (external oscillator).
4
UW
MIN 2.56 0.5 0.5
TYP
MAX 307.2 390 390
UNITS kHz s s ms ms ms kHz kHz
130.86 133.53 136.20 157.03 160.23 163.44 20510/fEOSC (in kHz) 19.2 fEOSC/8 45 250 250 1.23 1.25 1.28 192/fEOSC (in kHz) 24/fESCK (in kHz) 0 0 0 50 200 15 50 50 150 150 150 55 2000
Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 24-Bit Data Output Time External SCK 24-Bit Data Output Time CS to SDO Low Z CS to SDO High Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SCK Hold After CS
% kHz ns ns ms ms ms ns ns ns ns ns ns ns ns
(Note 10) (Note 9) (Note 5)
q q q q q q
Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation, the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: VREF = FSSET - ZSSET. The minimum input voltage is limited to - 0.3V and the maximum to VCC + 0.3V. Note 15: VCC (DC) = 4.1V, VCC (AC) = 2.8VP-P.
24212f
LTC2421/LTC2422 TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error (3V Supply)
10 8 6 4 VCC = 3V VREF = 2.5V 10 8 6 4
ERROR (ppm)
ERROR (ppm)
ERROR (ppm)
2 0 -2 -4 -6 -8 -10 0 0.5 1.5 2.0 1.0 INPUT VOLTAGE (V) 2.5
24212 G01
TA = -55C, -45C, 25C, 90C
Positive Extended Input Range Total Unadjusted Error (3V Supply)
10 8 6 4
ERROR (ppm)
VCC = 3V VREF = 2.5V
ERROR (ppm)
2 0 -2 -4 -6 -8 -10 2.50 2.55 2.60 2.65 2.70 INPUT VOLTAGE (V) 2.75 2.80 TA = -55C, -45C, 25C, 90C
2 0 -2 -4 -6 -8 -10 0 1 3 2 INPUT VOLTAGE (V) 4 5
24212 G05
ERROR (ppm)
Negative Extended Input Range Total Unadjusted Error (5V Supply)
10 8 6 4 ERROR (ppm) 2 0 -2 -4 -6 -8 -10 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 INPUT VOLTAGE (V)
24212 G07
VCC = 5V VREF = 5V
TA = 25C TA = 90C TA = -45C
ERROR (ppm)
TA = -55C
4 2 0 -2 -4 -6 -8 -10 5.00 TA = 90C 5.05 TA = 25C TA = -55C TA = -45C
OFFSET ERROR (ppm)
UW
24212 G04
INL (3V Supply)
VCC = 3V VREF = 2.5V
Negative Extended Input Range Total Unadjusted Error (3V Supply)
10 8 6 4 2 0 -2 -4 TA = -55C VCC = 3V VREF = 2.5V TA = 90C TA = 25C TA = -45C
2 0 -2 -4 -6 -8 -10 0 0.5 1.5 2.0 1.0 INPUT VOLTAGE (V) 2.5
24212 G02
TA = -55C, -45C, 25C, 90C
-6 -8 -10 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 INPUT VOLTAGE (V)
24212 G03
Total Unadjusted Error (5V Supply)
10 8 6 4 VCC = 5V VREF = 5V 10 8 6 4 2 0 -2 -4 -6 -8 -10
INL (5V Supply)
VCC = 5V VREF = 5V
TA = -55C, -45C, 25C, 90C
TA = -55C, -45C, 25C, 90C
0
1
3 2 INPUT VOLTAGE (V)
4
5
24212 G06
Positive Extended Input Range Total Unadjusted Error (5V Supply)
10 8 6 VCC = 5V VREF = 5V
150
Offset Error vs Reference Voltage
VCC = 5V TA = 25C
120
90
60
30
0
5.10 5.15 5.20 INPUT VOLTAGE (V)
5.25
5.30
0
1
3 4 2 REFERENCE VOLTAGE (V)
5
24212 G09
24212 G08
24212f
5
LTC2421/LTC2422 TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs Reference Voltage
60 50 VCC = 5V TA = 25C 10
RMS NOISE (ppm OF VREF)
OFFSET ERROR (ppm)
40 30 20 10 0 0 1 2 3 4 REFERENCE VOLTAGE (V) 5
24212 G10
0
RMS NOISE (ppm)
Noise Histogram
350 VCC = 5 =5 V 300 VREF 0 IN =
5.00
NUMBER OF READINGS
200 150 100 50 0 -2
RMS NOISE (ppm)
250
2.50
OFFSET ERROR (ppm)
4 2 0 OUTPUT CODE (ppm)
Full-Scale Error vs Temperature
10 VCC = 5V VREF = 5V VIN = 5V 0 -25
FULL-SCALE ERROR (ppm)
FULL-SCALE ERROR (ppm)
5
FULL-SCALE ERROR (ppm)
0
-5
-10 -55 -30
70 -5 20 45 TEMPERATURE (C)
6
UW
6
24212 G13
Offset Error vs VCC
VREF = 2.5V TA = 25C 10.0
RMS Noise vs VCC
VREF = 2.5V TA = 25C
5
7.5
5.0
-5
2.5
-10 2.7 3.2 3.7 4.2 VCC (V) 4.7 5.2 5.5
24212 G11
0 2.7 3.2 3.7 4.2 VCC (V) 4.7 5.2 5.5
24212 G12
RMS Noise vs Code Out
VCC = 5V VREF = 5V VIN = 0.3V TO 5.3V TA = 25C 10
Offset Error vs Temperature
VCC = 5V VREF = 5V VIN = 0V
3.75
5
0
1.25
-5
0 0 7FFFF CODE OUT (HEX) FFFFF
24212 G14
-10 -55 -30
70 -5 20 45 TEMPERATURE (C)
95
120
24212 G15
Full-Scale Error vs Reference Voltage
10
Full-Scale Error vs VCC
VREF = 2.5V VIN = 2.5V TA = 25C
5
-50 -75 -100 -125 -150 VCC = 5V VIN = VREF 0 1 2 3 4 REFERENCE VOLTAGE (V) 5
24212 G17
0
-5
-10 2.7 3.2 3.7 4.2 VCC (V) 4.7 5.2 5.5
24212 G18
95
120
24212 G16
24212f
LTC2421/LTC2422 TYPICAL PERFOR A CE CHARACTERISTICS
Conversion Current vs Temperature
230 220
SUPPLY CURRENT (A)
VCC = 5.5V
SUPPLY CURRENT (A) REJECTION (dB)
210 200 VCC = 4.1V 190 180 170 160 150 - 55 -30 -5 70 45 20 TEMPERATURE (C) 95 120 VCC = 2.7V
Rejection vs Frequency at VCC
-20 VCC = 4.1V VIN = 0V T = 25C -40 F A = 0 O
REJECTION (dB) REJECTION (dB) 0
-60
REJECTION (dB)
-80
-100
-120
1
50
150 200 100 FREQUENCY AT VCC (Hz)
Rejection vs Frequency at VIN
-60 -70 -80
REJECTION (dB)
REJECTION (dB)
-90 -100 -110 -120 -130
REJECTION (dB)
-140 -120 15100 -12 -8 -4 0 4 8 12 INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
24212 G25
UW
Sleep Current vs Temperature
30
0
Rejection vs Frequency at VCC
VCC = 4.1V VIN = 0V -20 TA = 25C FO = 0 -40 -60 -80
20
VCC = 2.7V VCC = 5V
10
-100
0 -55 -30
-120
-5 20 45 70 TEMPERATURE (C)
95
120
1
100 10k FREQUENCY AT VCC (Hz)
1M
24212 G23
24212 G19
24212 G20
Rejection vs Frequency at VCC
VCC = 4.1V VIN = 0V -20 TA = 25C FO = 0 -40 -60 -80 0 -20 -40 -60 -80
Rejection vs Frequency at VIN
VCC = 5V VREF = 5V VIN = 2.5V FO = 0
-100 -120 15200 15250 15300 15350 15400 15450 15500 FREQUENCY AT VCC (Hz)
24212 G22
-100 -120 1 50 100 150 200 FREQUENCY AT VIN (Hz) 250
24212 G24
250
24212 G21
Rejection vs Frequency at VIN
0 -20 -40 -60 -80 VCC = 5V VREF = 5V VIN = 2.5V FO = 0
0 -20 -40 -60 -80 -100 -120
Rejection vs Frequency at VIN
-100 SAMPLE RATE = 15.36kHz 2% 15200 15300 15400 FREQUENCY AT VIN (Hz) 15500
24212 G26
-140 0 fS/2 INPUT FREQUENCY
24212 G27
fS
24212f
7
LTC2421/LTC2422 TYPICAL PERFOR A CE CHARACTERISTICS
INL vs Output Rate
20 VCC = 5V VREF = 5V FO = EXTERNAL TUE RESOLUTION (BITS) 20
18 TUE RESOLUTION (BITS)
18
EFFECTIVE RESOLUTION (BITS)
16
TA = -45C TA = 25C
14 TA = 90C 12
10
0
10 20 30 40 50 60 70 80 90 100 OUTPUT RATE (Hz)
24212 G28
PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pin 6) with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. FSSET (Pin 2): Full-Scale Set Input. This pin defines the full-scale input value. When VIN = FSSET, the ADC outputs full scale (FFFFFH). The total reference voltage is FSSET - ZSSET. CH0, CH1 (Pins 4, 3): Analog Input Channels. The input voltage range is - 0.125 * VREF to 1.125 * VREF. For VREF > 2.5V, the input voltage range may be limited by the absolute maximum rating of - 0.3V to VCC + 0.3V. Conversions are performed alternately between CH0 and CH1 for the LTC2422. Pin 4 is a No Connect (NC) on the LTC2421. ZSSET (Pin 5): Zero-Scale Set Input. This pin defines the zero-scale input value. When VIN = ZSSET, the ADC outputs zero scale (00000H). GND (Pin 6): Ground. Shared pin for analog ground, digital ground, reference ground and signal ground. Should be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground in a single-point grounding system. CS (Pin 7): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW on CS wakes up the ADC. A LOW-to-HIGH transition on this pin disables the SDO digital output. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 8): Three-State Digital Output. During the data output period, this pin is used for serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin can be used as a conversion status output. The conversion status can be observed by pulling CS LOW.
8
UW
INL vs Output Rate
VCC = 3V VREF = 2.5V FO = EXTERNAL
Resolution vs Output Rate
24
22
16 TA = -45C 14 TA = 25C 12 TA = 90C
20
10
0
10 20 30 40 50 60 70 80 90 100 OUTPUT RATE (Hz)
24212 G29
VCC = 5V 18 V REF = 5V TA = 25C fO = EXTERNAL TA = 90C STANDARD DEVIATION TA = -45C OF 100 SAMPLES 16 25 75 0 7.5 100 50 OUTPUT RATE (Hz)
24212 G30
U
U
U
24212f
LTC2421/LTC2422
PIN FUNCTIONS
SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the data output period. In the External Serial Clock Operation mode, SCK is used as digital input for the external serial interface. An internal pull-up current source is automatically activated in Internal Serial Clock Operation mode. The Serial Clock mode is determined by the level applied to SCK at power up and the falling edge of CS. FO (Pin 10): Frequency Control Pin. Digital input that controls the ADC's notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter's first null is located at 50Hz. When the FO pin is connected to GND (FO = 0V), the converter uses its internal oscillator and the digital filter's first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its clock and the digital filter first null is located at a frequency fEOSC/2560.
FUNCTIONAL BLOCK DIAGRA
VCC GND
VIN

ADC SERIAL INTERFACE DECIMATING FIR
VREF
DAC
TEST CIRCUITS
VCC 3.4k
SDO 3.4k CLOAD = 20pF
Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z
24212 TC01
W
U
U
U
U
U
INTERNAL OSCILLATOR AUTOCALIBRATION AND CONTROL
FO (INT/EXT)
SDO SCK CS
24212 FD
SDO CLOAD = 20pF
Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z
24212 TC02
24212f
9
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
The LTC2421/LTC2422 are pin compatible with the LTC2401/LTC2402. The devices are designed to allow the user to incorporate either device in the same design with no modifications. While the LTC2421/LTC2422 output word length is 24 bits (as opposed to the 32-bit output of the LTC2401/LTC2402), its output clock timing can be identical to the LTC2401/LTC2402. As shown in Figure 1, the LTC2421/LTC2422 data output is concluded on the falling edge of the 24th serial clock (SCK). In order to maintain drop-in compatibility with the LTC2401/LTC2402, it is possible to clock the LTC2421/LTC2422 with an additional 8 serial clock pulses. This results in 8 additional output bits which are always logic HIGH. Converter Operation Cycle The LTC2421/LTC2422 are low power, delta-sigma analog-to-digital converters with an easy to use 3-wire serial interface. Their operation is simple and made up of three states. The converter operating cycle begins with the conversion, followed by the sleep state and concluded with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), a serial clock (SCK) and a chip select (CS). Initially, the LTC2421/LTC2422 perform a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by an order of magnitude if CS is HIGH. The part remains in the sleep state as long as CS is logic HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state.
CS 8 SCK 8 8 8 (OPTIONAL)
SDO
EOC = 1
EOC = 0
CONVERSION
SLEEP
Figure 1. LTC2421/LTC2422 Compatible Timing with the LTC2401/LTC2402
24212f
10
U
Once CS is pulled LOW and SCK rising edge is applied, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK, see Figure 4. The data output state is concluded once 24 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS and SCK pins, the LTC2421/LTC2422 offer several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section.
CONVERT SLEEP 1 CS AND SCK 0 DATA OUTPUT
24212 F02
W
UU
Figure 2. LTC2421/LTC2422 State Transition Diagram
DATA OUT 4 STATUS BITS 20 DATA BITS DATA OUTPUT
EOC = 1 LAST 8 BITS ALWAYS 1 CONVERSION
24212 F01
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
Conversion Clock
A major advantage delta-sigma converters offer over conventional type converters is an on-chip digital filter (commonly known as Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics. In order to reject these frequencies in excess of 110dB, a highly accurate conversion clock is required. The LTC2421/LTC2422 incorporate an on-chip highly accurate oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2421/ LTC2422 reject line frequencies (50Hz or 60Hz 2%) a minimum of 110dB. Ease of Use The LTC2421/LTC2422 data output has no latency, filter settling or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing an analog input voltage is easy. The LTC2421/LTC2422 perform offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2421/LTC2422 automatically enter an internal reset state when the power supply voltage VCC drops below approximately 2.2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection which is performed at the initial power-up. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with duration of approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2421/LTC2422 start a normal conversion cycle and follows the normal succession of states described
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above. The first conversion result following POR is accurate within the specifications of the device. Reference Voltage Range The LTC2421/LTC2422 can accept a reference voltage (VREF = FSSET - ZSSET) from 0V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter's effective resolution. On the other hand, a reduced reference voltage will improve the overall converter INL performance. The recommended range for the LTC2421/LTC2422 voltage reference is 100mV to VCC. Input Voltage Range The converter is able to accommodate system level offset and gain errors as well as system level overrange situations due to its extended input range, see Figure 3. The LTC2421/LTC2422 convert input signals within the extended input range of - 0.125 * VREF to 1.125 * VREF (VREF = FSSET - ZSSET). For large values of VREF (VREF = FSSET - ZSSET), this range is limited by the absolute maximum voltage range of - 0.3V to (VCC + 0.3V). Beyond this range, the input ESD protection devices begin to turn on and the errors due to the input leakage current increase rapidly. Input signals applied to VIN may extend below ground by - 300mV and above VCC by 300mV. In order to limit any
VCC + 0.3V FSSET + 0.12VREF FSSET ABSOLUTE MAXIMUM INPUT RANGE NORMAL INPUT RANGE EXTENDED INPUT RANGE ZSSET ZSSET - 0.12VREF -0.3V (VREF = FSSET - ZSSET)
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Figure 3. LTC2421/LTC2422 Input Range
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
fault current, a resistor of up to 5k may be added in series with the VIN pin without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between this series resistance and the VIN pin as low as possible; therefore, the resistor should be located as close as practical to the VIN pin. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Analog Input/Reference Current section. In addition, a series resistor will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2421/LTC2422 serial output data stream is 24 bits long. The first 4 bits represent status information indicating the sign, selected channel, input range and conversion state. The next 20 bits are the conversion result, MSB first. Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 22 (second output bit) for the LTC2422, this bit is LOW if the last conversion was performed on CH0 and HIGH for CH1. This bit is always LOW for the LTC2421. Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. The sign bit changes state during the zero code. Bit 20 (fourth output bit) is the extended input range (EXR) indicator. If the input is within the normal input range
CS
BIT 23 SDO Hi-Z SCK EOC
BIT 22 CH0/CH1
BIT 21 SIG
1 SLEEP
2
Figure 4. Output Data Timing
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0 VIN VREF, this bit is LOW. If the input is outside the normal input range, VIN > VREF or VIN < 0, this bit is HIGH. The function of these bits is summarized in Table 1.
Table 1. LTC2421/LTC2422 Status Bits
Input Range VIN > VREF 0 < VIN VREF VIN = 0+/0 - VIN < 0 Bit 23 EOC 0 0 0 0 Bit 22 CH0/CH1 *0/1 *0/1 *0/1 *0/1 Bit 21 SIG 1 1 1/0 0 Bit 20 EXR 1 0 0 1 *Bit 22 displays the channel number for the LTC2422. Bit 22 is always 0 for the LTC2421
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Bit 19 (fifth output bit) is the most significant bit (MSB). Bits 19-0 are the 20-bit conversion result MSB first. Bit 0 is the least significant bit (LSB). Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 4. Whenever CS is HIGH, SDO remains high impedance and any SCK clock pulses are ignored by the internal data out shift register. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 23rd SCK and may be latched on the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating a new conversion cycle has been initiated. This bit serves as EOC (Bit 23) for the next conversion cycle. Table 2 summarizes the output data format.
BIT 20 EXT
BIT 19 MSB
BIT 4
BIT 0 LSB20
3
4
5
19
20
24 CONVERSION
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DATA OUTPUT
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
Input Voltage VIN > 9/8 * VREF 9/8 * VREF VREF + 1LSB VREF 3/4VREF + 1LSB 3/4VREF 1/2VREF + 1LSB 1/2VREF 1/4VREF + 1LSB 1/4VREF 0+/0 - -1LSB -1/8 * VREF VIN < -1/8 * VREF Bit 23 EOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 22* CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 CH0/CH1 Bit 21 SIG 1 1 1 1 1 1 1 1 1 1 1/0** 0 0 0
Table 2. LTC2421/LTC2422 Output Data Format
Bit 20 EXR 1 1 1 0 0 0 0 0 0 0 0 1 1 1 Bit 19 MSB 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Bit 18 0 0 0 1 1 0 0 1 1 0 0 1 1 1 Bit 17 0 0 0 1 0 1 0 1 0 1 0 1 1 1 Bit 16 1 1 0 1 0 1 0 1 0 1 0 1 0 0 Bit 15 1 1 0 1 0 1 0 1 0 1 0 1 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... Bit 0 LSB 1 1 0 1 0 1 0 1 0 1 0 1 0 0
*Bit 22 is always 0 for the LTC2421 **The sign bit changes state during the 0 code.
As long as the voltage on the VIN pin is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any input value from - 0.125 * VREF to 1.125 * VREF. For input voltages greater than 1.125 * VREF, the conversion result is clamped to the value corresponding to 1.125 * VREF. For input voltages below - 0.125 * VREF, the conversion result is clamped to the value corresponding to - 0.125 * VREF. Frequency Rejection Selection (FO Pin Connection) The LTC2421/LTC2422 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz 2% or 60Hz 2%. For 60Hz rejection, FO (Pin 10) should be connected to GND (Pin 6) while for 50Hz rejection the FO pin should be connected to VCC (Pin 1). The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected.
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When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source, the LTC2421/ LTC2422 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz (1Hz notch frequency) to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2421/LTC2422 provide better than 110dB normal mode rejection in a frequency range fEOSC/ 2560 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/ 2560 is shown in Figure 5. Whenever an external clock is not present at the FO pin, the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2421/ LTC2422 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
-60 -70 -80 REJECTION (dB) -90 -100 -110 -120 -130
-140 -12 -8 -4 0 4 8 12 INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
24212 F05
Figure 5. LTC2421/LTC2422 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC
external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. Table 3 summarizes the duration of each state as a function of FO. SERIAL INTERFACE The LTC2421/LTC2422 transmit the conversion results and receives the start of conversion command through a
Table 3. LTC2421/LTC2422 State Duration
State CONVERT Operating Mode Internal Oscillator FO = LOW (60Hz Rejection) FO = HIGH (50Hz Rejection) External Oscillator
FO = External Oscillator with Frequency fEOSC kHz (fEOSC/2560 Rejection) FO = LOW/HIGH (Internal Oscillator) FO = External Oscillator with Frequency fEOSC kHz
SLEEP DATA OUTPUT Internal Serial Clock
External Serial Clock with Frequency fSCK kHz
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synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state, it is used to read the conversion result. Serial Clock Input/Output (SCK) The serial clock signal present on SCK (Pin 9) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2421/LTC2422 create their own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition is detected at the CS pin. If SCK is HIGH or floating at power-up or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode. Serial Data Output (SDO) The serial data output pin, SDO (Pin 8), drives the serial data during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS (Pin 7) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial
Duration 133ms 160ms 20510/fEOSCs As Long As CS = HIGH Until CS = 0 and SCK As Long As CS = LOW But Not Longer Than 1.28ms (24 SCK cycles) As Long As CS = LOW But Not Longer Than 192/fEOSCms (24 SCK cycles) As Long As CS = LOW But Not Longer Than 24/fSCKms (24 SCK cycles)
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS = 0. While in the sleep state, the device is in a LOW power state if CS is HIGH. Chip Select Input (CS) The active LOW chip select, CS (Pin 7), is used to test the conversion status and to enable the data output transfer as described in the previous sections. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2421/LTC2422 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs with CS = 0). Finally, CS can be used to control the free-running modes of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert at the maximum output rate selected by FO. Tying a capacitor to CS will reduce the output rate and power dissipation by a factor proportional to the capacitor's value, see Figures 13 to 15. SERIAL INTERFACE TIMING MODES The LTC2421/LTC2422's 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion and autostart. The following sections describe each of
Table 4. LTC2421/LTC2422 Interface Timing Modes
SCK Source External External Internal Internal Internal
Configuration External SCK, Single Cycle Conversion External SCK, 2-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 2-Wire I/O, Continuous Conversion Internal SCK, Autostart Conversion
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these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 4 for a summary. External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 6. The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the device automatically enters the sleep state once the conversion is complete. While in the sleep state, power is reduced an order of magnitude if CS is HIGH. When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. Data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. On the 24th falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress.
Conversion Cycle Control CS and SCK SCK CS Continuous CEXT Data Output Control CS and SCK SCK CS Internal Internal Connection and Waveforms Figures 6, 7 Figure 8 Figures 9, 10 Figure 11 Figure 12
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling
2.7V TO 5.5V 1F 1 VCC
REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET - 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET - ZSSET) 0V TO FSSET - 100mV
CS TEST EOC SDO Hi-Z Hi-Z TEST EOC TEST EOC
BIT 23 EOC
BIT 22 CH0/CH1
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
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Figure 6. External Serial Clock, Single Cycle Operation
2.7V TO 5.5V 1F 1 VCC LTC2422 REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET - 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET - ZSSET) 0V TO FSSET - 100mV 2 3 4 5 FSSET CH1 CH0 ZSSET SCK SDO CS GND 9 8 7 6 3-WIRE SERIAL I/O FO 10
VCC
CS TEST EOC TEST EOC TEST EOC
BIT 0 SDO EOC
Hi-Z
Hi-Z
Hi-Z
SCK (EXTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
24212 F07
Figure 7. External Serial Clock, Reduced Data Output Length
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CS HIGH anytime between the first rising edge and the 24th falling edge of SCK, see Figure 7. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion.
VCC
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FO
10
LTC2422 2 3 4 5 FSSET CH1 CH0 ZSSET SCK SDO CS GND 9 8 7 6
= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
3-WIRE SERIAL I/O
BIT 21 SIG
BIT 20 EXR
BIT 19 MSB
BIT 18
BIT 4
BIT 0 LSB20
Hi-Z
= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
BIT 23 EOC
BIT 22 CH0/CH1
BIT 21 SIG
BIT 20 EXR
BIT 19 MSB
BIT 9
BIT 8
Hi-Z
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 8. CS may be permanently tied to ground (Pin 6), simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion enters the low power sleep state. On the falling edge of EOC, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 24th falling edge of SCK, SDO
2.7V TO 5.5V 1F 1
REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET - 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET - ZSSET) 0V TO FSSET - 100mV
CS
BIT 23 SDO EOC
BIT 22 CH0/CH1
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
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Figure 8. External Serial Clock, CS = 0 Operation
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goes HIGH (EOC = 1) indicating a new conversion has begun. Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 9. In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to prevent the device from exiting the low power sleep state, CS must be pulled
VCC
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VCC LTC2422
FO
10
= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
2 3 4 5
FSSET CH1 CH0 ZSSET
SCK SDO CS GND
9 8 7 6 2-WIRE SERIAL I/O
BIT 21 SIG
BIT 20 EXR
BIT 19 MSB
BIT 18
BIT 4
BIT 0 LSB20
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET - 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET - ZSSET) 0V TO FSSET - 100mV BIT 23 EOC
BIT 22 CH0/CH1
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
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Figure 9. Internal Serial Clock, Single Cycle Operation
HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 23s if the device is using its internal oscillator (F0 = logic LOW or HIGH). If FO is driven by an external oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH, and a new conversion starts. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling
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VCC 2.7V TO 5.5V 1F 1 VCC LTC2422 2 3 4 5 FSSET CH1 CH0 ZSSET SCK SDO CS GND 9 8 7 6 FO 10
VCC
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= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
10k
BIT 21 SIG
BIT 20 EXR
BIT 19 MSB
BIT 18
BIT 4
BIT 0 LSB20
TEST EOC
Hi-Z
Hi-Z
CS HIGH anytime between the first and 24th rising edge of SCK, see Figure 10. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2421/LTC2422's internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2421/LTC2422's internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode.
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APPLICATIO S I FOR ATIO
REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET - 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET - ZSSET) 0V TO FSSET - 100mV
> tEOCtest CS TEST EOC TEST EOC
BIT 0 SDO Hi-Z EOC Hi-Z
Hi-Z
Hi-Z
SCK (INTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
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Figure 10. Internal Serial Clock, Reduced Data Output Length
A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin. Internal Serial Clock, 2-Wire I/O, Continuous Conversion This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 11. CS may be permanently tied to ground (Pin 6), simplifying the user interface or isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. An internal
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VCC 2.7V TO 5.5V 1F 1 VCC LTC2422 2 3 4 5 FSSET CH1 CH0 ZSSET SCK SDO CS GND 9 8 7 6 FO 10
VCC
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= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
10k
BIT 23 EOC
BIT 22 CH0/CH1
BIT 21 SIG
BIT 20 EXR
BIT 19 MSB
BIT 18
BIT 8
TEST EOC
Hi-Z
weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion.
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET - 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET - ZSSET) 0V TO FSSET - 100mV CS
SDO
BIT 23 EOC
BIT 22 CH0/CH1
BIT 21 SIG
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
24212 F11
Figure 11. Internal Serial Clock, Continuous Operation
Internal Serial Clock, Autostart Conversion This timing mode is identical to the internal serial clock, 2-wire I/O described above with one additional feature. Instead of grounding CS, an external timing capacitor is tied to CS. While the conversion is in progress, the CS pin is held HIGH by an internal weak pull-up. Once the conversion is complete, the device enters the low power sleep state and an internal 25nA current source begins discharging the capacitor tied to CS, see Figure 12. The time the converter spends in the sleep state is determined by the value of the external timing capacitor, see Figures 13 and 14. Once the voltage at CS falls below an internal threshold (1.4V), the device automatically begins outputting data. The data output cycle begins on the first rising edge of SCK and ends on the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. After the 24th rising edge, CS is pulled HIGH and a new conversion is immediately started. This is useful in applications requiring periodic monitoring and ultralow power. Figure 15 shows the average supply current as a function of capacitance on CS.
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2.7V TO 5.5V 1F 1 VCC LTC2422 2 3 4 5 FSSET CH1 CH0 ZSSET SCK SDO CS GND 9 8 7 6 FO 10
VCC
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VCC = INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
10k
BIT 20 EXR
BIT 19 MSB
BIT 18
BIT 4
BIT 0 LSB20
It should be noticed that the external capacitor discharge current is kept very small in order to decrease the converter power dissipation in the sleep state. In the autostart mode, the analog voltage on the CS pin cannot be observed without disturbing the converter operation using a regular oscilloscope probe. When using this configuration, it is important to minimize the external leakage current at the CS pin by using a low leakage external capacitor and properly cleaning the PCB surface. The internal serial clock mode is selected every time the voltage on the CS pin crosses an internal threshold voltage. An internal weak pull-up at the SCK pin is active while CS is discharging; therefore, the internal serial clock timing mode is automatically selected if SCK is floating. It is important to ensure there are no external drivers pulling SCK LOW while CS is discharging. DIGITAL SIGNAL LEVELS The LTC2421/LTC2422's digital interface is easy to use. Its digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100s. However, some considerations are required
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET - 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET - ZSSET) 0V TO FSSET - 100mV
VCC CS GND BIT 23 SDO Hi-Z EOC BIT 22 BIT 21 SIG Hi-Z BIT 0
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2420 F12
Figure 12. Internal Serial Clock, Autostart Operation
7 6
SUPPLY CURRENT (ARMS)
300 250 200 VCC = 3V 150 100 50 VCC = 5V
5
tSAMPLE (SEC)
SUPPLY CURRENT (ARMS)
4 3 2 VCC = 5V 1 0 1 10 100 VCC = 3V 1000 10000 CAPACITANCE ON CS (pF) 100000
0 1 10 100 1000 10000 CAPACITANCE ON CS (pF) 100000
24212 F15
24212 F13
Figure 13. CS Capacitance vs tSAMPLE
Figure 14. CS Capacitance vs Output Rate
to take advantage of exceptional accuracy and low supply current. The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state.
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VCC 2.7V TO 5.5V 1F 1 VCC LTC2422 2 3 4 5 FSSET CH1 CH0 ZSSET SCK SDO CS GND 9 8 7 6 CEXT FO 10
VCC
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= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
10k
300 250 200 VCC = 3V 150 100 50 0 1 10 100 1000 10000 CAPACITANCE ON CS (pF) 100000
24212 F15
VCC = 5V
Figure 15. CS Capacitance vs Supply Current
In order to preserve the LTC2421/LTC2422's accuracy, it is very important to minimize the ground path impedance which may appear in series with the input and/or reference signal and to reduce the current which may flow through this path. The GND pin should be connected to a low
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21
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
resistance ground plane through a minimum length trace. The use of multiple via holes is recommended to further reduce the connection resistance. In an alternative configuration, the GND pin of the converter can be the single-point-ground in a single point grounding system. The input signal ground, the reference signal ground, the digital drivers ground (usually the digital ground) and the power supply ground (the analog ground) should be connected in a star configuration with the common point located as close to the GND pin as possible. The power supply current during the conversion state should be kept to a minimum. This is achieved by restricting the number of digital signal transitions occurring during this period. While a digital input signal is in the range 0.5V to (VCC - 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the LTC2421/LTC2422 power supply current may increase even if the signal in question is at a valid logic level. For micropower operation and in order to minimize the potential errors due to additional ground pin current, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC - 0.4V)]. Severe ground pin current disturbances can also occur due to the undershoot of fast digital input signals. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2421/LTC2422. For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance.
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Parallel termination near the LTC2421/LTC2422 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 and 56 placed near the driver or near the LTC2421/LTC2422 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. Driving the Input and Reference The analog input and reference of the typical delta-sigma analog-to-digital converter are applied to a switched capacitor network. This network consists of capacitors switching between the analog input (VIN), ZSSET (Pin 5) and FSSET (Pin 2). The result is small current spikes seen at both VIN and VREF. A simplified input equivalent circuit is shown in Figure 16. The key to understanding the effects of this dynamic input current is based on a simple first order RC time constant model. Using the internal oscillator, the LTC2421/ LTC2422's internal switched capacitor network is clocked at 153,600Hz corresponding to a 6.5s sampling period. Fourteen time constants are required each time a capacitor is switched in order to achieve 1ppm settling accuracy. Therefore, the equivalent time constant at VIN and VREF should be less than 6.5s/14 = 460ns in order to achieve 1ppm accuracy.
VCC IREF(LEAK) VREF IREF(LEAK) IIN VIN IIN(LEAK) RSW 5k GND
24212 F16
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RSW 5k
VCC IIN(LEAK) RSW 5k AVERAGE INPUT CURRENT: IIN = 0.25(VIN - 0.5 * VREF)fCEQ CEQ 1pF (TYP)
SWITCHING FREQUENCY f = 153.6kHz FOR INTERNAL OSCILLATOR (fO = LOGIC LOW OR HIGH) f = fEOSC FOR EXTERNAL OSCILLATORS
Figure 16. LTC2421/LTC2422 Equivalent Analog Input Circuit
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
Input Current (VIN)
If complete settling occurs on the input, conversion results will be uneffected by the dynamic input current. If the settling is incomplete, it does not degrade the linearity performance of the device. It simply results in an offset/ full-scale shift, see Figure 17. To simplify the analysis of input dynamic current, two separate cases are assumed: large capacitance at VIN (CIN > 0.01F) and small capacitance at VIN (CIN < 0.01F).
TUE
OFFSET ERROR (ppm)
ZSSET VIN
Figure 17. Offset/Full-Scale Shift
RSOURCE VIN INTPUT SIGNAL SOURCE CIN CPAR 20pF LTC2421/ LTC2422
24212 F17
Figure 18. An RC Network at VIN
50 VCC = 5V VREF = 5V VIN = 0V TA = 25C
FULL-SCALE ERROR (ppm)
40
OFFSET ERROR (ppm)
30
20
CIN = 0pF CIN = 100pF CIN = 1000pF CIN = 0.01F
10
0
1
10
1k 100 RSOURCE ()
10k
100k
24212 F19
Figure 19. Offset vs RSOURCE (Small C)
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If the total capacitance at VIN (see Figure 18) is small (< 0.01F), relatively large external source resistances (up to 80k for 20pF parasitic capacitance) can be tolerated without any offset/full-scale error. Figures 19 and 20 show a family of offset and full-scale error curves for various small valued input capacitors (CIN < 0.01F) as a function of input source resistance. For large input capacitor values (CIN > 0.01F), the input spikes are averaged by the capacitor into a DC current. The gain shift becomes a linear function of input source resistance independent of input capacitance, see Figures 21 and 22. The equivalent input impedance is 16.6M. This results in 150nA of input dynamic current at the extreme values of VIN (VIN = 0V and VIN = VREF, when VREF = 5V). This corresponds to a 0.3ppm shift in offset and full-scale readings for every 10 of input source resistance.
35 30 25 CIN = 22F CIN = 10F CIN = 1F CIN = 0.1F CIN = 0.01F CIN = 0.001F FSSET
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20 VCC = 5V VREF = 5V 15 VIN = 0V TA = 25C 10 5 0 0 200 400 600 RSOURCE () 800 1000
24212 F20
Figure 20. Offset vs RSOURCE (Large C)
5 0 -5 -10 -15 -20 -25 -30 -35 0 CIN = 22F CIN = 10F CIN = 1F CIN = 0.1F CIN = 0.01F CIN = 0.001F 200 400 600 RSOURCE () 800 1000
24212 F21
VCC = 5V VREF = 5V VIN = 0V TA = 25C
Figure 21. Full-Scale Error vs RSOURCE (Large C)
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
10 0 FULL-SCALE ERROR (ppm)
FULL-SCALE ERROR (ppm)
-10 -20 -30 -40 -50 1 VCC = 5V VREF = 5V VIN = 5V TA = 25C 10 CIN = 0.01F CIN = 0pF CIN = 100pF CIN = 1000pF
100 1k RSOURCE ()
10k
100k
24212 F22
Figure 22. Full-Scale Error vs RSOURCE (Small C)
FULL-SCALE ERROR (ppm)
In addition to the input current spikes, the input ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (100nA max), results in a fixed offset shift of 10V for a 10k source resistance. The effect of input leakage current is evident for CIN = 0 in Figures 19 and 22. A leakage current of 3nA results in a 150V (30ppm) error for a 50k source resistance. As RSOURCE gets larger, the switched capacitor input current begins to dominate. Reference Current (VREF) Similar to the analog input, the reference input has a dynamic input current. This current has negligible effect on the offset. However, the reference current at VIN = VREF is similar to the input current at full-scale. For large values of reference capacitance (CVREF > 0.01F), the full-scale error shift is 0.03ppm/ of external reference resistance independent of the capacitance at VREF, see Figure 23. If the capacitance tied to VREF is small (CVREF < 0.01F), an input resistance of up to 80k (20pF parasitic capacitance at VREF) may be tolerated, see Figure 24. Unlike the analog input, the integral nonlinearity of the device can be degraded with excessive external RC time constants tied to the reference input. If the capacitance at node VREF is small (CVREF < 0.01F), the reference input can tolerate large external resistances without reduction in INL, see Figure 25. If the external capacitance is large (CVREF > 0.01F), the linearity will be degraded by
INL ERROR (ppm)
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60 50 40 CVREF = 22F CVREF = 10F CVREF = 1F CVREF = 0.1F CVREF = 0.01F CVREF = 0.001F 30 VCC = 5V VREF = 5V 20 VIN = 5V TA = 25C 10 0 -10 0 200 400 600 800 RESISTANCE AT VREF () 1000
24212 F23
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Figure 23. Full-Scale Error vs RVREF (Large C)
500
VCC = 5V = 5V V 400 VREF 5V IN = TA = 25C 300
CVREF = 1000pF CVREF = 100pF
200 CVREF = 0.01F 100 0 -100 -200 1 10 100 1k 10k RESISTANCE AT VREF () 100k
24212 F24
CVREF = 0pF
Figure 24. Full-Scale Error vs RVREF (Small C)
50
VCC = 5V = 5V V 40 T REF 25C A= 30 CVREF = 1000pF
20 CVREF = 100pF 10 CVREF = 0.01F 0 -10 -20 1 10 100 1k 10k RESISTANCE AT VREF () 100k
24212 F25
CVREF = 0pF
Figure 25. INL Error vs RVREF (Small C)
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LTC2421/LTC2422
APPLICATIO S I FOR ATIO
0.015ppm/ independent of capacitance at VREF, see Figure 26. In addition to the dynamic reference current, the VREF ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a fixed full-scale shift of 10V for a 10k source resistance.
10 8 6 CVREF = 22F CVREF = 10F CVREF = 1F CVREF = 0.1F CVREF = 0.01F CVREF = 0.001F VCC = 5V VREF = 5V TA = 25C
REJECTION (dB)
INL ERROR (ppm)
4 2 0 -2 -4 -6 -8 -10 0
200
400 600 800 RESISTANCE AT VREF ()
1000
24212 F26
Figure 26. INL Error vs RVREF (Large C)
ANTIALIASING One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2421/LTC2422 significantly simplify antialiasing filter requirements. The digital filter provides very high rejection except at integer multiples of the modulator sampling frequency (fS), see Figure 27. The modulator sampling frequency is 256 * FO, where FO is the notch frequency (typically 50Hz or 60Hz). The bandwidth of signals not rejected by the digital filter is narrow ( 0.2%) compared to the bandwidth of the frequencies rejected. As a result of the oversampling ratio (256) and the digital filter, minimal (if any) antialias filtering is required in front of the LTC2421/LTC2422. If passive RC components are placed in front of the LTC2421/LTC2422, the input dynamic current should be considered (see Input Current section). In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of input dynamic current.
VREF VIN GND LTC2421 LTC2422 SCK SDO CS DTR CTS RTS PC SERIAL PORT
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0 -20 -40 -60 -80 -100 -120 -140 0 fS/2 INPUT FREQUENCY
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fS
Figure 27. Sinc4 Filter Rejection
The modulator contained within the LTC2421/LTC2422 can handle large-signal level perturbations without saturating. Signal levels up to 40% of VREF do not saturate the analog modulator. These signals are limited by the input ESD protection to 300mV below ground and 300mV above VCC. Simple Basic Program for Interfacing to the LTC2421/LTC2422
24212 F28
Figure 28
"TINY.BAS V1.0 Copyright (C) 2000 by J. A. Dutra and LTC, All rights reseved' NOTE this program generates 32 SCK's for compatibility to 24-bit parts 'For use with most LTC24xy demo boards designed for the PC Com Port, QBASIC 'Outputs are chan%,signneg%,d2400 (magnitude), PPM, and v (volts) CLS : ON ERROR GOTO 4970 cport = 1: REM INPUT "com port number "; cport GOSUB 1900: timestart$ = TIME$ mcr% = port + 4: msr% = port + 6 COLOR 15: LOCATE 3, 1: PRINT "Hit any key to stop... FOR np = 1 TO 2000: OUT port, c0%: NEXT np: 'Power Via TxD DO: '-------------------------START LOOP here-------24212f
";
25
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
nummeas = nummeas + c1% OUT mcr%, c0%: 'Initialize SCLK=0 k1 = km: d2400 = 0: chan% = c0%: signneg% = c0% FOR bita% = 31 TO 0 STEP -1: v31 = 1 148 GOSUB 2200: v31 = v31 + 1 150 IF bita% = 31 THEN GOTO 152 ELSE 156 152 IF dfrm% = c0% THEN GOTO 156
LOCATE 2, 2: PRINT "Scan#="; nummeas; " "; DATE$; " "; TIME$;
155 IF v31 > 2 THEN LOCATE 16, 16: OUT port, c0%: PRINT "waiting for eoc": IF v31 < 20000 THEN IF dfrm% = c1% THEN GOTO 148 IF dfrm% = 1 THEN LOCATE 17, 16: PRINT "Timed out on EOC,not fatal" FOR bs = 1 TO 32: ' never got an eoc => clock it 32 times GOSUB 2000: NEXT bs: GOTO 1800 156 LOCATE 16, 16: PRINT" ": GOSUB 2000
IF bita% = 30 THEN 161 ELSE 171 ' CHANNEL BIT !!!!!!!!!!!!!!! 161 IF dfrm% = c1% THEN chan% = c1%: ch1% = c0% IF dfrm% = c0% THEN chan% = c0%: ch1% = ch1% + c1% IF ch1% > c4% THEN GOSUB 3700: ch1% = c1% 171 IF bita% = 29 THEN IF dfrm% = c0% THEN signneg% = c1%: ' NEG IF bita% <= 28 THEN d2400 = d2400 + (dfrm% * k1): k1 = k1 / c2% NEXT bita%: k1 = 1: digin% = c0%: 'MATH BELOW 1600 PPM = (d2400 / km) * kn: rw% = 6: hz% = (chan% * 20) + 1 IF signneg% = c1% THEN 1700 ELSE 1705 1700 IF d2400 <> c0% THEN PPM = (PPM - 2000000) 1705 LOCATE rw%, hz%: PRINT PPM; " "; : LOCATE rw%, hz% + 11: PRINT "PPM"; LOCATE rw% + 1, (chan% * 20) + 1: GOSUB 3800: 'THIS WORKS! 1800 LOOP WHILE INKEY$ = "": REM Works with "DO" GOTO 5000 'rem END!!-------------- Subs follow !!----------------!!! 1900 'ESSENTIAL INITIALIZATIONS REM set some constants, since they can be accessed much faster LET c128% = 128: c64% = 64: c32% = 32: c16% = 16: c8% = 8: c4% = 4 LET c3% = 3: c2% = 2: c1% = 1: c0% = 0: km = (2 ^ 30) - 1: kn = 1000000 IF cport = 2 THEN OPEN "COM2:300,N,8,1,CD0,CS0,DS0,OP0,RS" FOR RANDOM AS #1: port = (&H2F8) IF cport = 1 THEN OPEN "COM1:300,N,8,1,CD0,CS0,DS0,OP0,RS" FOR RANDOM AS #1: port = (&H3F8)
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LOCATE 5, 21: PRINT "CHANNEL 1": LOCATE 5, 2: PRINT "CHANNEL 0" FOR n% = port TO port + 7: OUT n%, 0: NEXT n%: 'Init UART regs CLOSE #1: DEF SEG = 0: RETURN '-------------------------------------2000 'SUB read MSR AND RETURN data dfrm% INTERFACE x3% = INP(msr%) AND c16%: OUT mcr%, c1% GOSUB 3000: OUT mcr%, c0% 2040 IF x3% = c16% THEN dfrm% = c1% ELSE dfrm% = c0% OUT mcr%, c0%: RETURN '--------------------------------------------2200 'SUB READ THE DATA BIT dfrm% does NOT change sclock x3% = INP(msr%) AND C16%: GOTO 2040: RETURN'---------------3000 REM delay sub !!!!!!!!!! FOR n8% = 0 TO 1: OUT port, c0%: NEXT n8%: RETURN: '---------3700 FOR n = 6 TO 9: LOCATE n, 20 PRINT " ": NEXT n: RETURN'--------------------------3800 'SUB to convert PPM into Volts and print it v = PPM * (5 / 1000000): v1 = v * 1000000: hz% = (chan% * 20) + 12 IF v <= .1 THEN PRINT v1; " "; : LOCATE rw% + 1, hz%: PRINT "uV " IF v > .1 THEN PRINT v; " "; : LOCATE rw% + 1, hz%: PRINT "Volts"; RETURN'---------------------------------------------------------------4970 PRINT "ERROR !!!!!!!!!!!!!!!" 5000 PRINT : LOCATE 18, 1: PRINT "Ending!!": PRINT "Hit any key to exit." PRINT "Start ="; timestart$; " End = "; TIME$; " # samples ="; nummeas CLOSE #1: END
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Single Ended Half-Bridge Digitizer with Reference and Ground Sensing Sensors convert real world phenomena (temperature, pressure, gas levels, etc.) into a voltage. Typically, this voltage is generated by passing an excitation current through the sensor. The wires connecting the sensor to the ADC form parasitic resistors RP1 and RP2. The excitation current also flows through parasitic resistors RP1 and RP2, as shown in Figure 29. The voltage drop across these parasitic resistors leads to systematic offset and full-scale errors. In order to eliminate the errors associated with these parasitic resistors, the LTC2421/LTC2422 include a full-scale set input (FS SET ) and a zero-scale set input (ZSSET). As shown in Figure 30, the FSSET pin acts as a zero current full-scale sense input. Errors due to parasitic
24212f
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
resistance RP1 in series with the half-bridge sensor are removed by the FSSET input to the ADC. The absolute fullscale output of the ADC (data out = FFFFFHEX ) will occur at VIN = VB = FSSET, see Figure 31. Similarly, the offset errors due to RP2 are removed by the ground sense input ZSSET. The absolute zero output of the ADC (data out = 00000HEX) occurs at VIN = VA = ZSSET. Parasitic resistors RP3 to RP5 have negligible errors due to the 1nA (typ) leakage current at pins FSSET, ZSSET and VIN. The wide dynamic input range (- 300mV to 5.3V) and low noise (1.2ppm RMS) enable the LTC2421 or the LTC2422 to directly digitize the output of the bridge sensor. The LTC2422 is ideal for applications requiring continuous monitoring of two input sensors. As shown in Figure 32, the LTC2422 can monitor both a thermocouple temperature probe and a cold junction temperature sensor. Absolute temperature measurements can be performed with a variety of thermocouples using digital cold junction compensation.
RP1
+ V - FULL-SCALE ERROR + SENSOR OUTPUT -
00000H 12.5% UNDER RANGE ZSSET
24212 F29
IEXCITATION
SENSOR
RP2
+ V - OFFSET ERROR
ADC DATA OUT
Figure 29. Errors Due to Excitation Currents
2.7V TO 5.5V LTC2422 1 12k COLD JUNCTION THERMISTOR 100 2 3 4 5 VCC FSSET CH1 CH0 ZSSET
+
THERMOCOUPLE
Figure 32. Isolated Temperature Measurement
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1 RP1 VB RP3 IDC 0 IEXCITATION RP4 IDC 0 VA RP2 RP5 IDC 0 VCC 2 LTC2421 FSSET SCK VIN SDO CS 5 6 ZSSET GND FO 10
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9 8 7 3-WIRE SPI INTERFACE
3
Figure 30. Half-Bridge Digitizer with Zero-Scale and Full-Scale Sense
FFFFFH
12.5% EXTENDED RANGE
FSSET VIN
24212 F31
Figure 31. Transfer Curve with Zero-Scale and Full-Scale Set
FO SCK SDO CS GND
10 9 8 7 6 PROCESSOR
24212 F32
-
ISOLATION BARRIER
27
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
The selection between CH0 and CH1 is automatic. Initially, after power-up, a conversion is performed on CH0. For each subsequent conversion, the input channel selection is alternated. Embedded within the serial data output is a status bit indicating which channel corresponds to the conversion result. If the conversion was performed on CH0, this bit (Bit 22) is LOW and is HIGH if the conversion was performed on CH1 (see Figure 33). There are no extra control or status pins required to perform the alternating 2-channel measurements. The LTC2422 only requires two digital signals (SCK and SDO). This simplification is ideal for isolated temperature measurements or systems where minimal control signals are available. Pseudo Differential Applications Generally, designers choose fully differential topologies for several reasons. First, the interface to a 4- or 6-wire bridge is simple (it is a differential output). Second, they require good rejection of line frequency noise. Third, they typically look at a small differential signal sitting on a large common mode voltage; they need accurate measurements of the differential signal independent of the common mode input voltage. Many applications currently using fully differential analog-to-digital converters for any of the above reasons may migrate to a pseudo differential conversion using the LTC2422. Direct Connection to a Full Bridge The LTC2422 interfaces directly to a 4- or 6-wire bridge, as shown in Figure 34. The LTC2422 includes a FSSET and a ZSSET for sensing the excitation voltage directly across the bridge. This eliminates errors due to excitation currents flowing through parasitic resistors. The LTC2422 also includes two single ended input channels which can tie directly to the differential output of the bridge. The two
***
SCK
SDO EOC CH1
CH1 DATA OUT EOC CH0
Figure 33. Embedded Selected Channel Indicator
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conversion results may be digitally subtracted yielding the differential result. The LTC2422's single ended rejection of line frequencies (2%) and harmonics is better than 110dB. Since the device performs two independent single ended conversions each with > 110dB rejection, the overall common mode and differential rejection is much better than the 80dB rejection typically found in other differential input delta-sigma converters. In addition to excellent rejection of line frequency noise, the LTC2422 also exhibits excellent single ended noise rejection over a wide range of frequencies due to its 4th order sinc filter. Each single ended conversion independently rejects high frequency noise (> 60Hz). Care must be taken to insure noise at frequencies below 15Hz and at multiples of the ADC sample rate (15,360Hz) are not present. For this application, it is recommended the LTC2422 is placed in close proximity to the bridge sensor in order to reduce the noise injected into the ADC input. By performing three successive conversions (CH0-CH1-CH0), the drift and low frequency noise can be measured and compensated for digitally.
IEXCITATION IDC = 0 2 5V 1 VCC FSSET LTC2422 9 SCK CH1 CH0 SDO CS FO ZSSET GND 6
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350
350 3 4
8 7 10
3-WIRE SPI INTERFACE
350
350 IDC = 0 5
Figure 34. Pseudo Differential Strain Guage Application
***
CH0 DATA OUT
24212 F33
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
The absolute accuracy (less than 10 ppm total error) of the LTC2422 enables extremely accurate measurement of small signals sitting on large voltages. Each of the two pseudo differential measurements performed by the LTC2422 is absolutely accurate independent of the common mode voltage output from the bridge. The pseudo differential result obtained from digitally subtracting the two single ended conversion results is accurate to within the noise level of the device (3VRMS) times the square root of 2, independent of the common mode input voltage. Typically, a bridge sensor outputs 2mV/V full scale. With a 5V excitation, this translates to a full-scale output of 10mV. Divided by the RMS noise of 8.4V(= 6V * 1.414), this circuit yields 1190 counts with no averaging or amplification. If more counts are required, several conversions may be averaged (the number of effective counts is increased by a factor of square root of 2 for each doubling of averages). An RTD Temperature Digitizer RTDs used in remote temperature measurements often have long lead lengths between the ADC and RTD sensor. These long lead lengths lead to voltage drops due to excitation current in the interconnect to the RTD. This voltage drop can be measured and digitally removed using the LTC2422 (see Figure 35). The excitation current (typically 200A) flows from the ADC through a long lead length to the remote temperature sensor (RTD). This current is applied to the RTD, whose
IEXCITATION = 200A
+ Pt VRTD 100 -
R1 IEXCITATION = 200A
IDC = 0 R2
Figure 35. RTD Remote Temperature Measurement
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resistance changes as a function of temperature (100 to 400 for 0C to 800C). The same excitation current flows back to the ADC ground and generates another voltage drop across the return leads. In order to get an accurate measurement of the temperature, these voltage drops must be measured and removed from the conversion result. Assuming the resistance is approximately the same for the forward and return paths (R1 = R2), the auxiliary channel on the LTC2422 can measure this drop. These errors are then removed with simple digital correction. The result of the first conversion on CH0 corresponds to an input voltage of VRTD + R1 * IEXCITATION. The result of the second conversion (CH1) is - R1 * IEXCITATION. Note, the LTC2422's input range is not limited to the supply rails, it has underrange capabilities. The device's input range is - 300mV to VREF + 300mV. Adding the two conversion results together, the voltage drop across the RTD's leads are cancelled and the final result is VRTD. An Isolated, 20-Bit Data Acquisition System The LTC1535 is useful for signal isolation. Figure 36 shows a fully isolated, 20-bit differential input A/D converter implemented with the LTC1535 and LTC2422. Power on the isolated side is regulated by an LT1761-5.0 low noise, low dropout micropower regulator. Its output is suitable for driving bridge circuits and for ratiometric applications. During power-up, the LTC2422 becomes active at VCC = 2.3V, while the isolated side of the LTC1535 must wait for VCC2 to reach its undervoltage lockout threshold of 4.2V.
5V 1 2 VCC FSSET LTC2422 25 5k 4 SCK CH0 SDO CS CH1 FO ZSSET GND 6
24212 F35
W
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9 8 7 10 3-WIRE SPI INTERFACE
1000pF 3
25
5k 0.1F
5
29
LTC2421/LTC2422
APPLICATIO S I FOR ATIO
Below 4.2V, the LTC1535's driver outputs Y and Z are in a high impedance state, allowing the 1k pull-down to define the logic state at SCK. When the LTC2422 first becomes active, it samples SCK; a logic "0" provided by the 1k pull-down invokes the external serial clock mode. In this mode, the LTC2422 is controlled by a single clock line from the nonisolated side of the barrier, through the LTC1535's driver output Y. The entire power-up sequence,
1/2 BAT54C
T1
1/2 BAT54C
"SDO"
"SCK" LOGIC 5V
RO ST1 RE DE DI VCC1 10F 10V TANT
ST2 LTC1535 G1 G2
+
1
1
1
2
ISOLATION BARRIER
Figure 36. Complete, Isolated 20-Bit Data Acquisition System
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from the time power is applied to VCC1 until the LT1761's output has reached 5V, is approximately 1ms. Data returns to the nonisolated side through the LTC1535's receiver at RO. An internal divider on receiver input B sets a logic threshold of approximately 3.4V at input A, facilitating communications with the LTC2422's SDO output without the need for any external components.
LT1761-5
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+
10F 16V TANT 1F
IN SHDN
OUT 10F BYP
+
GND
10F 10V TANT
2
+
2
VCC2 A B Y Z
10F 10V TANT LTC2422 FO SCK SDO CS GND VCC FSSET CH1 CH0 ZSSET
10F CERAMIC
2
1k
1 2
= LOGIC COMMON = FLOATING COMMON
2 2
24212 F36
T1 = COILTRONICS CTX02-14659 OR SIEMENS B78304-A1477-A3
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LTC2421/LTC2422
PACKAGE I FOR ATIO
5.23 (.206) MIN
0.50 3.05 0.38 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) 0.13 0.05 (.005 .002)
MSOP (MS) 1001
0.50 (.0197) NOTE: TYP 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005) 3.2 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF DETAIL "A" 0 - 6 TYP 12345 0.53 0.01 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.86 (.034) REF 4.88 0.10 (.192 .004) 3.00 0.102 (.118 .004) NOTE 4
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LTC2421/LTC2422
TYPICAL APPLICATIO
Figure 37 shows the block diagram of a demo circuit (contact LTC for a demonstration) of a multichannel isolated temperature measurement system. This circuit decodes an address to select which LTC2422 receives a 24-bit burst of SCK signal. All devices independently
D1
SCK
SD0
DIN (ADDRESS OR COUNTER)
Figure 37. Mulitchannel Isolated Temperature Measurement System
RELATED PARTS
PART NUMBER LT1019 LTC1050 LT1236A-5 LTC1391 LT1461-2.5 LTC1535 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2413 LTC2415 LTC2420 LTC2424/LTC2428 LTC2430 LTC2431 DESCRIPTION Precision Bandgap Reference, 2.5V, 5V Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V 8-Channel Multiplexer Precision Micropower Voltage Reference Isolated RS485 Transceiver 24-Bit, No Latency ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ADC in MSOP 4-/8-Channel, 24-Bit, No Latency ADC 24-Bit, No Latency ADC 24-Bit, Fully Differential, No Latency ADC 20-Bit, No Latency ADC in SO-8 4-/8-Channel, 20-Bit, No Latency ADC 20-Bit, Fully Differential, No Latency ADC in SSOP-16 24-Bit, Fully Differential, No Latency ADC in MS10 COMMENTS 3ppm/C Drift, 0.05% Max No External Components 5V Offset, 1.6VP-P Noise 0.05% Max, 5ppm/C Drift Low RON: 45, Low Charge Injection Serial Interface 50A Supply Current, 3ppm/C Drift 2500VRMS Isolation 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.6ppm Noise, 4ppm INL, Pin Compatible with the LTC2421/LTC2422 4ppm INL, 10ppm Total Unadjusted Error, 200A Simultaneous 50Hz and 60Hz Rejection, 0.16ppm Noise 15Hz Output Rate at 60Hz Rejection, Pin Conpatible with the LTC2410 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408 0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200A 0.29ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A
24212f LT/TP 0202 2K * PRINTED IN USA
32
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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convert either the thermal couple output or the thermistor cold junction output. After each conversion, the devices enter their sleep state and wait for the SCK signal before clocking out data and beginning the next conversion.
LTC1535 A RE Y R0 SDO SCK ZSSET VCC FSSET CH1 CH0 LTC2422 HC138 D1 LTC1535 A RE Y R0 SDO SCK ZSSET VCC FSSET CH1 CH0 LTC2422
+ -
2500V
D1 HC138 RE Y R0 SEE FIGURE 34 FOR THE COMPLETE CIRCUIT LTC1535 A SDO SCK
VCC FSSET CH1 CH0
LTC2422
ZSSET
HC595 ADDRESS LATCH
24212 F37
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2002

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